1. Field of the Invention
This invention relates in general to a manufacturing process for semiconductor devices, and more specifically relates to a manufacturing process for semiconductor devices having common gate, source and well structures.
2. Description of Related Art
FIGS. 1A through 1C schematically illustrate cross-sectional views of manufacturing process for forming a conventional semiconductor device having a common gate, source and well.
Referring to FIG. 1A, a well 102 and isolation regions 104 are formed within a substrate 100 by which structures the active region of the device is defined. A gate oxide 106 and a gate 108 are subsequently formed above the active region.
As shown in FIG. 1B, a P.sup.- lightly doped region 110 serving as a pocket region and an N.sup.- lightly doped region 112 serving as the lightly doped drain (LDD) of the device thereafter are subsequently formed within the well 102. The depth of the pocket region 110 is deeper than that of the LDD region 112. A spacer 114 is formed surrounding the gate 108 by which the source/drain region can be defined thereafter. N-type ions of higher concentration than in doped regions 110 and 112 are implanted into the doped region 110 and 112 to form N.sup.+ doped regions 116a and 116b serving as the drain and the source, respectively. A P.sup.+ doped region 118 is formed within the well 102 as shown in FIG. 1B, serving as the well pick-up region 118 of the well 102. Silicide layers 120a, 120b, 120c and 120d are deposited on the surfaces of the drain 116a, the source 116b, the gate 108 and the well pick-up region 118, respectively.
FIG. 1C schematically depicts the final structure of the device. A dielectric layer 122 is deposited on the whole surface of the substrate 100 and then contacts are formed within the dielectric layer 122, through which contacts the gate, source and well pick-up region are exposed. Afterwards, tungsten plugs 124a, 124b and 124c are formed within the contacts and then a metal layer is deposited on the dielectric layer 122 to serve as an interconnect to electrically connect the gate 108, source 116b and well pick-up region 118.
As seen in the foregoing description, the conventional method for forming semiconductor device having common gate, source and well uses three plugs 124a, 124b and 124c to connect the gate 108, source 116b and well 102 respectively, which 3 plugs increase the size of the device. Furthermore, in order not to increase the area of the device due to using the three plugs 124a, 124b and 124c to connect the gate 108, source 116b and well pick-up region 118, each area of the gate 108, source 116b and well pick-up region 118 has to be as small as possible, which reduces the alignment error tolerance. Therefore, the difficulty of forming a common gate, source and well in the conventional method is increased as well and affects the yield.